MIPS Goes Open Source (eetimes.com) 70
Junko Yoshida, writing for EETimes: Without question, 2018 was the year RISC-V genuinely began to build momentum among chip architects hungry for open-source instruction sets. That was then. By 2019, RISC-V won't be the only game in town. Wave Computing (Campbell, Calif.) announced Monday (Dec. 17) that it is putting MIPS on open source, with MIPS Instruction Set Architecture (ISA) and MIPS' latest core R6 available in the first quarter of 2019. Art Swift, hired by Wave this month as president of its MIPS licensing business, described the move as critical to accelerate the adoption of MIPS in an ecosystem.
Going open source is "a big plan" that Wave CEO Derek Meyer, a MIPS veteran, has been quietly fostering since Wave acquired MIPS Technologies in June, explained Swift. Swift himself is a MIPS alumnus who worked at the company as a vice president of marketing and business development for four years. Wave, which styles itself as a tech startup poised to bring "AI and deep learning from the datacenter to the edge," sees MIPS as a key to advancing Wave's AI into a host of uses and applications. Included in MIPS instruction sets are extensions such as SIMD (single instruction, multiple data) and DSP. Swift promised that MIPS will bring to the open-source community "commercial-ready" instruction sets with "industrial-strength" architecture. "Chip designers will have opportunities to design their own cores based on proven and well tested instruction sets for any purposes," said Swift.
Going open source is "a big plan" that Wave CEO Derek Meyer, a MIPS veteran, has been quietly fostering since Wave acquired MIPS Technologies in June, explained Swift. Swift himself is a MIPS alumnus who worked at the company as a vice president of marketing and business development for four years. Wave, which styles itself as a tech startup poised to bring "AI and deep learning from the datacenter to the edge," sees MIPS as a key to advancing Wave's AI into a host of uses and applications. Included in MIPS instruction sets are extensions such as SIMD (single instruction, multiple data) and DSP. Swift promised that MIPS will bring to the open-source community "commercial-ready" instruction sets with "industrial-strength" architecture. "Chip designers will have opportunities to design their own cores based on proven and well tested instruction sets for any purposes," said Swift.
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MIPS (what the article is about) is not RISC-V.
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Not to sound too disparaging. But Open Source is often the waste bin of dead technology.
Well we worked hard on it, it wasn't profitable. Might as well open source it, and see if anyone else would have any value with it.
There are some successes such as Mozilla which Netscape Dumped its Netscape Communicator Code to the Open Source, because they were not making money from it. But there are a lot of other things that just never did anything with. Because it was garbage.
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I think MIPS might very well fall into that category too. Mozilla survived not because Seamonkey/gekko were any good at the time compared to IE. They were not; for all the problems IE 4/5 had; it was better. Mozilla technology was good enough though and solid enough to be built on and made better. Nobody would have bother but for the fact the MS had essentially abandon the idea of making a contemporary web browser available on anything other then 32-bit Windows.
MIPS while a good design is really obsolet
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You're missing the big picture here. While SPARC and MIPS lost out to x86 they are both mature ISAs with many competing features to x86. For example they have their own SIMD implementations on the FPU. This will be a big boon to RISCV. One of the places where RISCV will find it hard to compete with x86 and ARM is that they both have some very important patented extensions. Intel beat its competitors not because x86 was technically better, but because they were able to catch the widespread consumer adoption
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Sure but any company with the means to actually fab those chips is going to take it and put their own custom spin on it so their MIPS chip is going to work differently to somebody else's MIPS chip. You just end up with a fragmented market.
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Intel beat its competitors not because x86 was technically better, but because they were able to catch the widespread consumer adoption in PCs which lead to them being able to outspend others in process node technology. Now that TSMC has caught up to them a great deal, the only other major performance hurdle are the ISA extensions and optimizations. If MIPS is truly FOSS then many of those mature features can be re-implemented into RISCV and earn a massive performance boost. Specifically the SIMD extensions and VPE (MIPS equivalent to hyper-threading) will be useful.
It was not only process technology. Intel's development budget was larger than all of the RISC developer budgets combined which allowed features like out-of-order execution. Development tools have improved but a high performance RISC design is not going to be significantly easier to produce than a high performance x86 design.
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Interesting place to put a period. And a weirdly bioinformatics slant on the technological life cycle.
I don't know about yours, but my copy of the Pythagorean theorem remains as rust-free as it ever was.
There are good ways, however, to incorporate intrinsic vice into your code base, to make sure that once it goes into the trash heap, it stays on the trash heap. One approach to this problem is to write your application on
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Well we worked hard on it, it wasn't profitable. Might as well open source it, and see if anyone else would have any value with it.
It's a fair criticism but in this case it's the non-altruistic motive: they want other people to maintain their tech for them.
Wave is a hardware neural net company. They bought MIPS so that they could have an ultra low power CPU to handle the basic overhead of an OS and dispatch training jobs to their custom ASIC. Since the MIPS CPU is nothing more than a necessary evil in their system, open sourcing means they maintain a healthy MIPS ecosystem to keep their CPU architecture from rotting and maybe even ev
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The CEO is a former MIPS CTO. They had already committed to a technology they were familiar with before MIPS came up for sale. They simply acquired the rights to technology they had already chosen.
They can now make an MIPS-AI CPU with their custom neural net hardware integrated with a MIPS CPU and sell a high quality, well understood and well supported CPU but with an added accelerator for AI tasks. It's similar to Nvidia's similar efforts, except Nvidia is pairing an ARM core as the necessary-evil-co
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Not to sound too disparaging. But Open Source is often the waste bin of dead technology.
Yep. The IT industry's equivalent of the movie industry's "If you can't make it good, make it 3D" is "If you can't make it successful, make it open source".
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Can be the case, but in this one in particular is most likely a matter of marketing.
With all the spectre and meltdown inferno roaring the x86 land, opening the source of your chip tells the potential clients that they can actually check themselves if the chip have problems or not, specially multibillionaire corporations.
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Let's see, what is running on a MIPS here (thing I can interact with):
- TV
- STB
- wireless accesspoints
- router
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We need MMIX (Score:2)
Pleeease!
What will you use for graphics? (Score:2)
Since Nintendo wonâ(TM)t make a classic mini N64 we can make our own with an open mips chip.
What's your graphics hardware going to look like?
Anyway, this is exciting whether it will let you knock off the N64's CPU or not. Like TFA says, MIPS is mature. It's not known for performance, but maybe this will be the shot in the ARM that it's looking for.
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MIPS was a performance architecture back in the 90s, and one of the first to have 64bit support. Many supercomputers were built using MIPS cpus at one time.
The move to 64bit could have been a real opportunity for MIPS, they've a tried and tested 64bit architecture that's been around since the early 90s with existing mature support from compilers and operating systems - and yet arm64 started from scratch and overtook them.
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"MIPS was a performance architecture back in the 90s,"
A lot of things were different back in the nineties. MIPS didn't scale.
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Available in configurations up to 512 processors:
https://en.wikipedia.org/wiki/... [wikipedia.org]
Seemed to scale pretty well...
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Available in configurations up to 512 processors:
https://en.wikipedia.org/wiki/ [wikipedia.org]...
Seemed to scale pretty well...
What you're missing there is that SGI built all the glue logic to make that possible, which resulted in some computers which yes were very powerful, but which were also very expensive per MIPS, ironically. SGI machines cost more per unit of performance than anything else, but also offered more performance than anything short of a Cray. That led to their use only in specific niche markets, and their eventual dying out as x86 processors left MIPS behind. (SGI did sell one PC at the end, but it was overpriced
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You could, but you cannot legally get the games.
Besides the mini-Nintendo stuff, is just an emulation of the ROMs not small version of the same hardware.
A lot of these older games, just won't work on newer TV's without some emulation. LCD and the other Digital TVs were based on Pixels. Older game the pixels were more based on timing, and artifacts, granted I am talking more about the old CGA displays and less about the Nintendo.
Then do it with third-party games (Score:2)
you cannot legally get the games.
Granted for first-party games. But it should be feasible for a sufficiently capitalized toy company to license 20 well-received third-party Nintendo 64 games from their publishers to make and sell a "Classic 64" console without Nintendo's help and without Nintendo's name on the box. At 8 to 32 MB per ROM, it'll fit comfortably on a board with 512 MB flash. Though the present source release does not include the Nintendo 64's RSP (vertex shader) and RDP (triangle filler), a high level emulation thereof would
Wasn't R6... (Score:1)
The FUBAR MIPS instruction set that wasn't backwards compatible with older MIPS code?
If so, why would anyone want to go BACK to MIPS when they can get a fresh architecture, or use an established one with backwards compatibility? What is the suppler, developer, or end user benefit when it has less software compatibility, no compelling differences, and no low cost desktop/development platform or implementation to run atop?
How nice? Not nice. (Score:3)
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SPARC has been GPL for years (Score:4, Informative)
SPARC has been GPL for years (Score:?)
by Anonymous Coward on Monday December 17, 2018 @03:51PM
Risc-V never was the only game in town; SPARC has been avaialable under the GPLv2 since 2006: https://en.wikipedia.org/wiki/OpenSPARC
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RISC-V scales down much further than SPARC. I terms of target market, RISC-V has qualities of the more configurable embedded cores like ARC [wikipedia.org] (weird that a Super Nintendo accelerator chip ended up in millions of SD memory cards) and Xtensa [wikipedia.org]. RISC-V wasn't really meant to compete with SPARC, and it only somewhat overlaps MIPS for application processors. Room for custom extensions for RISC-V are provided by the spec, so we already have DSP and crypto instructions on some fives.
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RISC-V scales down much further than SPARC.
ask google what happens when you use GPL code from oracle
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ask google what happens when you use GPL code from oracle
Well said. Best to avoid dealing with Oracle. They ruin Java and MySQL for the community. R.I.P. SPARC
Re: SPARC has been GPL for years (Score:2)
Not getting sued is easy. Just set your repository up on a server on the island they use as a tax haven and go completely anonymous with it.
There's no way they'd risk violating the anonymity by omerta, it would expose all the stuff they want kept secret and piss off the banks who have no official records of Oracle opening those other accounts.
Always use your enemy's bank account as a body shield.
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RISC-V is an open-source architecture. MIPS on open source threatens RISC-V more than MIPS threatens ARM.
As an architecture, MIPS occupies the high end of computing and ARM occupies the low end. The high end is high performance with high demand on energy. The low end is medium performance with low demand on energy.
RISC-V is an attempt to straddle both ends. RISC-V will not succeed in the low end because ARM is firmly entrenched there.
RISC-V has a chance at the high end, but MIPS is now positioned as an
Fujitsu Abandons SPARC (Score:1)
Fujitsu has decided to replace SPARC with ARM.
Re: SPARC has been GPL for years (Score:3)
This!
OpenSPARC cores have been used in the OpenPiton project [princeton.edu] from Princeton, building a scalable system (at least, more scalable than the crossbar-based T1) with their own memory subsystem.
And you know what? Last week they launched a new version of the project, replacing the OpenSPARC cores with the Ariane RISC-V core from PULP [pulp-platform.org] (ETH).
If MIPS launches their own open-source cores, no doubt somebody will implement them in their project. But they would need to be really good (in performance, MIPS/W or some othe
Great News!!! (Score:2)
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MIPS isn't going to replace your x86 desktop. MIPS certainly has been scaled up to high end computing [wikipedia.org] before, it's not really well suited to fast desktops running a small number of tightly coupled threads (very dependent on inter-processor cache performance)
If you think it is important to use an alternative, then take a look at getting a TALOS II [raptorcs.com]. It's a POWER9 based workstation that is pricey but not totally bananas. You do give up about 5% of performance [itjungle.com] on POWER9 when you apply the Spectre and Meltdown p
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All those SGI workstations must have been a figment of my imagination then?
MIPS can do just fine to replace an x86 desktop. It also works just fine in the embedded space too.
My routers at work have a 64 bit MIPS with 16 cores doing 1.8GHz (version of the silicon do 2.2GHz) with 16GB of DDR4 RAM. IT has a couple of SATA III ports on the SoC, and USB3. Do a version with less 10Gbps ports and some more PCI lanes for say an AMD GPU and that would do very nicely for my desktop thank you very much.
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All those SGI workstations must have been a figment of my imagination then?
Correct. You aren't going to see a favorable comparison between a late 1990's workstation and a 2018 desktop. A lot has changed in 20 years, not just in Si fabrication but in computer architecture as well.
My routers at work have a 64 bit MIPS with 16 cores doing 1.8GHz
I used to be a kernel developer for a Cavium-based product at Cisco. Cavium is a multicore MIPS architecture, early OCTEON chips had absolutely no cache protocol between cores, making it useless for assigning all cores to Linux. So no good SMP for that architecture. What you can do is run network processin
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Did you forget a sarcasm tag somewhere? MIPS is a puny joke compared to a desktop
CPU.
Re: Great News!!! (Score:2)
I dunno, SGI went bankrupt after moving from MIPS to Intel. It wasn't due to the extra horsepower dragging them along.
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IRIX in portable form factor? (Score:3)
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Probably not. Modern MIPS is not the same ISA as what SGI's machines used.
If there would be a modern MIPS chip that could run the older ISA in user-mode (like 386 code on a x86-64 system), I think it would be better to create a subsystem for IRIX on FreeBSD -- which is a more up-to-date foundation than IRIX' old kernel.
The FreeBSD kernel has a framework for foreign syscall interfaces, through which it already supports running e.g. Linux binaries natively.
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Somebody above referred to fond memories of writing MIPS assembler in school. I have fond memories of writing a MIPS compiler in school. :)
My Octane is celebrating ;-) (Score:2)
We really need a new architecture (Score:3)
Ideally, we need several.
But to really understand what works and why, you want examples.
I hope, now the Itanium 3 has been discontinued for a while, that and the Intel iWarp are open sourced. Doubt it, but one can always hope.
Between the MIPS, the T2, the GPLed SPARC, the RISC-V, the open source elements of the AMULET series and everything on Open Cores, we've a substantial body of knowledge on very large numbers of threads, very high performance, asynchronous computing and advanced ALU.
Throw in the two above as well and our understanding is almost complete.
IRIX (Score:2)