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Open Source IBM Hardware

OpenPower Foundation Releases a Friendly EULA For IBM's Power ISA RISC (phoronix.com) 28

Long-time Slashdot reader lkcl writes: Michael Larabel, of Phoronix, writes that the OpenPower Foundation has released a license agreement for Hardware Vendors to implement the Power ISA RISC instruction set in their processors. Hugh Blemings, the Director of OpenPower, was responsible for ensuring that the EULA is favourable and friendly towards Libre and Open Hardware projects and businesses.

Of particular interest is that IBM's massive patent portfolio is automatically granted, royalty-free as long as two conditions apply: firstly, the hardware must be fully and properly Power ISA compliant, and secondly, the implementor must not "try it on" as a patent troll.

Innovation in the RISC space just got a little more interesting.

"Amidst the fully free and open RISC-V ISA making headway into the computing market, and ARM feeling pressured to loosen up its licensing, it seems they figured that it's best to join the party early," argues Hackaday.
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OpenPower Foundation Releases a Friendly EULA For IBM's Power ISA RISC

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  • to China developing their own POWER implementation, just like they did with ALPHA [wikipedia.org]

    • to China developing their own POWER implementation, just like they did with ALPHA [wikipedia.org]

      Why is that exactly? Do you plan on buying Chinese military hardware or something?

    • How they could benefit from copying the POWER ISA and why would they wait until now? Seriously, there are better options (e.g. ARMv8 or RISC-V) and they already developed their ALPHA based one for military applications. They have nothing to gain from POWER.

      • It makes a pretty decent embedded processor.

        • It can be used for that but isn't its ISA much more complex than other RISC designs?
          • Re:to what end? (Score:4, Interesting)

            by Brett Buck ( 811747 ) on Sunday February 16, 2020 @04:43PM (#59733912)

            Yes, but there's extensive experience, support, infrastructure set up around it, which for many embedded processor uses, is frequently far more important than the guts of the instruction set.

            We have rack after rack of test setups for it, and emulators, its cheap and widely available, and everyone understands it. That's more important than optimization.

          • by _merlin ( 160982 )

            The core instruction set is pretty simple. It's just suffered from endless extensions, which aren't all present in every implementation. Extensions include:

            • 64-bit integer registers
            • Double-precision FPU
            • Single-precision FPU using integer registers
            • VMX/AltiVec 128-bit SIMD unit
            • VMX128 128-bit SIMD unit with more registers but fewer operations than regular VMX
            • VSX vector-scalar extension (lots of format conversion instructions, etc.)
        • Have power improved power consumption? (Pun intended)

          Osx migrated to Intel because g5 was too hot for a laptop.

      • RISC-V looks ok.

        The ARM and execution model assembly was always ugly. The history of how ARM got a foothold has nothing to do with it being better and everything to do with it being available as a licensable block at a time when other CPU vendors were not willing to play that game.

        I wouldn't touch POWER. Although I like the EIEIO instruction just for its name https://en.wikipedia.org/wiki/... [wikipedia.org].

        • ARM is "ugly" perhaps but it is easy to work with and gets the job done.

          The real advantage with RISC-V is only that the openness means you can get exactly what you want for a much lower cost without paying extra rent. Actually implementing anything looks about the same on any RISC-like system; unpainted metal ends up ugly.

        • by gtall ( 79522 )

          ARM has metastasized into an entire ecosystem. Also, some FPGAs have ARM cores within the FPGA fabric which makes it a nice combination for producing very targeted SoCs. Dunno how expensive the IP is, but it does exist if you've got the jack.

        • Although I like the EIEIO instruction just for its name https://en.wikipedia.org/wiki/... [wikipedia.org].

          For best performance, use the EIEIO with AIX Dog Threads:

          https://www.ibm.com/support/kn... [ibm.com]

        • by tlhIngan ( 30335 )

          The ARM and execution model assembly was always ugly. The history of how ARM got a foothold has nothing to do with it being better and everything to do with it being available as a licensable block at a time when other CPU vendors were not willing to play that game.

          Or it was a high performance low power processor, which is why Apple partnered with Acorn to develop it further and make it embeddable int he Newton.

          The Acorn RISC Machine processor back then was a clean, fairly performant 32-bit architecture use

          • Thanks for the history lesson. I was there in Cambridge as it was happening in the 90s.

            What people wanted was soft macros (I.E. RTL) of CPUs they already had OSs and GSM software for. Intel and moto said "no" followed by more "no" with an added dose of "no". Think 'feature phones' of the mid 90s.

            ARM only gave them hard macros but at least you could put it in your asic. The pin timing on the ARM7TDMI was horrible and I was always wrapping them in caches to get the thing to run without too many bus waits. The

      • by AHuxley ( 892839 )
        To open the move to consumer desktop and smartphone use.
        An entire nation moves away from NSA and GCHQ tech.
        No more paying for the West tech at any level per device sold.
      • Ok, Intel has not fixed all their speculative execution bugs yet, while other things have also popped up. Now ARM was infected by these 'borrowed' speed-ups, as was even IBM mainframe assembler was hit. Also many people do not trust management engines that have sneaked in,. and soon to be DRM lockdowns that also hide from everything. Thus a simple cpu with no hidden baggage, but shrunk down a lot Power was designed to offload I/O's etc, before memory got cheap, excluding fragmentation issues. Just add som
  • E.g. when the ($).($) eyes start lighting up again.

  • They figured it too late, many of us think. Power was open some time ago, and it didn't get the traction that Riscv has today. If RiscV does not "win" today, I do not see why Power would.

    • So what you're saying is that now that the product is nearly worthless there is very little risk for them in giving it away?

      Is this not industrial tradition?

    • by lkcl ( 517947 ) <lkcl@lkcl.net> on Sunday February 16, 2020 @04:01PM (#59733778) Homepage

      They figured it too late, many of us think. Power was open some time ago, and it didn't get the traction that Riscv has today. If RiscV does not "win" today, I do not see why Power would.

      Power already has decades-long established use: debian packages have existed for around 20 years for example. IBM and the other OpenPOWER Foundation members, particularly with Hugh's involvement, are going to be much more concerned about acting responsibly and "getting things right". RISC-V's primary focus is about attracting new high-profile well-funded members and ignoring all other considerations, even at the expense of ignoring Trademark Law's legal obligations and responsibilities.

      • I find the comment about trademark law surprising:
        Where have the people behind RISC-V violated trademarks?
        AFAIK RISC-V is a new instruction set and does not try to be compatible to other processors.

        • by lkcl ( 517947 ) <lkcl@lkcl.net> on Monday February 17, 2020 @05:32AM (#59735028) Homepage

          I find the comment about trademark law surprising:
          Where have the people behind RISC-V violated trademarks?

          ah you misunderstand: as a Trademark holder *themselves*, they are ignoring their legal obligations... *as* a Trademark Holder, namely that they have completely ignored - consistently and persistently - EIGHTEEN MONTHS of reasonable and in-good-faith requests for our team to be included in the *innovation* of RISC-V... without at the same time destroying the "Full Transparency" business objectives that go with being a Libre *business*. note: not a Libre "toy project" (which is already adequately covered by the RISC-V Specification) a Libre *BUSINESS*.

          it never occurred to the RISC-V Founders that someone would actually try to combine "Libre" with "Business". their assumption has always been, "if it's Libre it's a toy, they'll never in a million years raise the capital to bring a chip to market", and "if it's a business, they'll compromise on ethical considerations, sign NDAs, do whatever it takes to make money".

          at no time did they ever consider that someone might actually raise funds - through charitable donations - to meet *both* ethical considerations *and* get a chip out the door.

          unfortunately, by signing the RISC-V Membership Agreement, and by participating in the "secretive closed lists", this is a conflict of interest for us - one that is *literally* unique - and they have completely failed to even acknowledge this or enter into any kind of dialog or discussion.

          so by ignoring our repeated requests for participation and inclusion in the *innovation* (the enhancement of RISC-V Standards), the RISC-V Foundation is in direct contravention of their legal obligations under Trademark Law. if they continue down this path, they risk having the Trademark invalidated, or, worse, fall foul of anti-trust legislation.

          • Late answer, but I have just taken a look at the Membership Agreement, and at no point I could see an obligation for the foundation to adopt suggestions from the members. On the contrary:

            3.1. Contributions. Member may but is not required to make Contributions to the Foundation on behalf of itself and its Affiliates and Member acknowledges that the Foundation including any committee or subcommittee is not required to incorporate the Contribution or any part thereof into the RISC-V ISA.

            As far as I understand the Membership Agreement, it is mostly about making sure that the copyrights around RISC-V stay "Libre" and no member can establish a legal monopoly on RISC-V.

  • by Anonymous Coward
    I am just waiting for Oracle to Open Source Sparc64!

    Oh, it is aleady.

    People are just waiting for Larry Ellison to die before they would risk $1 on it.

    • by gtall ( 79522 )

      But before Uncle Larry goes to the Great Heaven for Jackasses, he'll be doing some damage here on earth first. He has some of his minions bypassing paying off congress critters and going directly the White House. Apparently, he's a big supporter of Republicans and now is attempting to get the alleged administration to crack down on privacy re the big tech companies like Apple, Microsoft, Amazon, and, wait for it, Google. He doesn't give rat's ass about privacy but he cares very much about Google. Naturally,

  • by sad_ ( 7868 )

    Does anybody know if the RISC-V platform can benefit from this?

Don't get suckered in by the comments -- they can be terribly misleading. Debug only code. -- Dave Storer

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